/*
 * Academic License - for use in teaching, academic research, and meeting
 * course requirements at degree granting institutions only.  Not for
 * government, commercial, or other organizational use.
 *
 * File: MCU_28335.c
 *
 * Code generated for Simulink model 'MCU_28335'.
 *
 * Model version                  : 1.4
 * Simulink Coder version         : 24.2 (R2024b) 21-Jun-2024
 * C/C++ source code generated on : Sun Dec  8 23:17:28 2024
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Texas Instruments->C2000
 * Code generation objectives: Unspecified
 * Validation result: Not run
 */

#include "MCU_28335.h"
#include "MCU_28335_private.h"
#include "rtwtypes.h"
#include <string.h>

/* Block signals (default storage) */
B_MCU_28335_T MCU_28335_B;

/* Block states (default storage) */
DW_MCU_28335_T MCU_28335_DW;

/* Real-time model */
static RT_MODEL_MCU_28335_T MCU_28335_M_;
RT_MODEL_MCU_28335_T *const MCU_28335_M = &MCU_28335_M_;
uint16_T MW_adcInitFlag = 0;

/* Hardware Interrupt Block: '<S1>/C28x Hardware Interrupt' */
void isr_int1pie1_task_fcn(void)
{
  if (1 == runModel) {
    /* Call the system: <S1>/Function-Call Subsystem */
    {
      /* RateTransition generated from: '<Root>/Application' */
      MCU_28335_B.TmpRTBAtApplicationOutport1 =
        MCU_28335_DW.TmpRTBAtApplicationOutport1_Buf;

      /* S-Function (c28xisr_c2000): '<S1>/C28x Hardware Interrupt' */

      /* Output and update for function-call system: '<S1>/Function-Call Subsystem' */

      /* S-Function (c280xpwm): '<S7>/ePWM4' */

      /*-- Update CMPA value for ePWM6 --*/
      {
        EPwm6Regs.CMPA.half.CMPA = (uint16_T)
          (MCU_28335_B.TmpRTBAtApplicationOutport1);
      }

      /* S-Function (c280xgpio_do): '<S7>/Digital Output1' incorporates:
       *  Constant: '<S7>/Constant4'
       */
      {
        if ((1U)) {
          GpioDataRegs.GPASET.bit.GPIO18 = 1U;
        } else {
          GpioDataRegs.GPACLEAR.bit.GPIO18 = 1U;
        }
      }

      /* End of Outputs for S-Function (c28xisr_c2000): '<S1>/C28x Hardware Interrupt' */
    }
  }
}

/* Model step function */
void MCU_28335_step(void)
{
  uint16_T tmp;

  /* S-Function (c280xadc): '<S6>/ADC' */
  {
    MCU_28335_B.ADC_o1 = (AdcRegs.ADCRESULT0) >> 4;
    MCU_28335_B.ADC_o2 = (AdcRegs.ADCRESULT1) >> 4;
    MCU_28335_B.ADC_o3 = (AdcRegs.ADCRESULT2) >> 4;
    MCU_28335_B.ADC_o4 = (AdcRegs.ADCRESULT3) >> 4;
    MCU_28335_B.ADC_o5 = (AdcRegs.ADCRESULT4) >> 4;
    AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1U;/* Sequencer reset*/
  }

  /* Chart: '<Root>/TimerBase' */
  if (MCU_28335_DW.tmr1msbase > 10U) {
    MCU_28335_DW.tmr1msbase = 0U;

    /* Outputs for Function Call SubSystem: '<Root>/Application' */
    /* Chart: '<S2>/TimerBase' */
    if (MCU_28335_DW.tmr10msbase > 100U) {
      MCU_28335_DW.tmr10msbase = 0U;

      /* Outputs for Function Call SubSystem: '<S2>/HeartBeats' */
      /* Switch: '<S11>/Switch' incorporates:
       *  Constant: '<S11>/Constant1'
       *  Constant: '<S11>/Constant2'
       *  Constant: '<S11>/Constant3'
       *  Delay: '<S11>/Delay'
       *  RelationalOperator: '<S11>/Relational Operator'
       *  Sum: '<S11>/Add1'
       *  Sum: '<S11>/Add2'
       */
      if (MCU_28335_DW.Delay_DSTATE <= 7000U) {
        MCU_28335_DW.Delay_DSTATE += 500U;
      } else {
        MCU_28335_DW.Delay_DSTATE -= 7500U;
      }

      /* End of Switch: '<S11>/Switch' */

      /* S-Function (c28xsci_tx): '<S10>/SCI Transmit' */
      {
        if (checkSCITransmitInProgressA != 1U) {
          checkSCITransmitInProgressA = 1U;
          int16_T errFlgHeader = NOERROR;
          int16_T errFlgData = NOERROR;
          int16_T errFlgTail = NOERROR;
          errFlgData = scia_xmit((uchar_T*)&MCU_28335_B.ADC_o2, 2, 2);
          checkSCITransmitInProgressA = 0U;
        }
      }

      /* S-Function (c280xgpio_do): '<S8>/Digital Output1' incorporates:
       *  Constant: '<S8>/Constant1'
       */
      {
        GpioDataRegs.GPCTOGGLE.bit.GPIO68 = (uint16_T)((1.0) != 0);
      }

      /* End of Outputs for SubSystem: '<S2>/HeartBeats' */
    } else {
      tmp = MCU_28335_DW.tmr10msbase + 1U;
      if (MCU_28335_DW.tmr10msbase + 1U > 255U) {
        tmp = 255U;
      }

      MCU_28335_DW.tmr10msbase = tmp;
    }

    /* End of Chart: '<S2>/TimerBase' */
    /* End of Outputs for SubSystem: '<Root>/Application' */
  } else {
    tmp = MCU_28335_DW.tmr1msbase + 1U;
    if (MCU_28335_DW.tmr1msbase + 1U > 255U) {
      tmp = 255U;
    }

    MCU_28335_DW.tmr1msbase = tmp;
  }

  /* End of Chart: '<Root>/TimerBase' */

  /* RateTransition generated from: '<Root>/Application' incorporates:
   *  Delay: '<S11>/Delay'
   */
  MCU_28335_DW.TmpRTBAtApplicationOutport1_Buf = MCU_28335_DW.Delay_DSTATE;
}

/* Model initialize function */
void MCU_28335_initialize(void)
{
  /* Registration code */

  /* initialize error status */
  rtmSetErrorStatus(MCU_28335_M, (NULL));

  /* block I/O */
  (void) memset(((void *) &MCU_28335_B), 0,
                sizeof(B_MCU_28335_T));

  /* states (dwork) */
  (void) memset((void *)&MCU_28335_DW, 0,
                sizeof(DW_MCU_28335_T));

  /* Start for S-Function (c280xadc): '<S6>/ADC' */
  if (MW_adcInitFlag == 0U) {
    InitAdc();
    MW_adcInitFlag = 1U;
  }

  config_ADC_A (4U, 12816U, 4U, 0U, 0U);

  /* SystemInitialize for S-Function (c28xisr_c2000): '<S1>/C28x Hardware Interrupt' incorporates:
   *  SubSystem: '<S1>/Function-Call Subsystem'
   */

  /* System initialize for function-call system: '<S1>/Function-Call Subsystem' */

  /* Start for S-Function (c280xpwm): '<S7>/ePWM2' */

  /*** Initialize ePWM2 modules ***/
  {
    /*-- Setup Time-Base (TB) Submodule --*/
    EPwm2Regs.TBPRD = 7500;

    /* -- Time-Base Control Register
       EPwm2Regs.TBCTL.bit.CTRMODE    = 2;          -- Counter Mode
       EPwm2Regs.TBCTL.bit.SYNCOSEL   = 3;          -- Sync output select
       EPwm2Regs.TBCTL.bit.PRDLD      = 0;          -- Shadow select
       EPwm2Regs.TBCTL.bit.PHSEN      = 0;          -- Phase load enable
       EPwm2Regs.TBCTL.bit.PHSDIR     = 0;          -- Phase Direction
       EPwm2Regs.TBCTL.bit.HSPCLKDIV  = 0;          -- High speed time pre-scale
       EPwm2Regs.TBCTL.bit.CLKDIV     = 0;          -- Timebase clock pre-scale
     */
    EPwm2Regs.TBCTL.all = (EPwm2Regs.TBCTL.all & ~0x3FBF) | 0x32;

    /* -- Time-Base Phase Register
       EPwm2Regs.TBPHS.half.TBPHS     = 0;          -- Phase offset register
     */
    EPwm2Regs.TBPHS.all = (EPwm2Regs.TBPHS.all & ~0xFFFF0000) | 0x0;
    EPwm2Regs.TBCTR = 0x0000;          /* Clear counter*/

    /*-- Setup Counter_Compare (CC) Submodule --*/
    /* -- Counter-Compare Control Register
       EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0;  -- Compare A block operating mode.
       EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0;  -- Compare B block operating mode.
       EPwm2Regs.CMPCTL.bit.LOADAMODE = 0;          -- Active compare A
       EPwm2Regs.CMPCTL.bit.LOADBMODE = 0;          -- Active compare A
     */
    EPwm2Regs.CMPCTL.all = (EPwm2Regs.CMPCTL.all & ~0x5F) | 0x0;
    EPwm2Regs.CMPA.half.CMPA = 5000;
    EPwm2Regs.CMPB = 6500;

    /*-- Setup Action-Qualifier (AQ) Submodule --*/
    EPwm2Regs.AQCTLA.all = 144;
    EPwm2Regs.AQCTLB.all = 513;

    /* -- Action-Qualifier Software Force Register
       EPwm2Regs.AQSFRC.bit.RLDCSF    = 0;          -- Reload from Shadow options
     */
    EPwm2Regs.AQSFRC.all = (EPwm2Regs.AQSFRC.all & ~0xC0) | 0x0;

    /* -- Action-Qualifier Continuous S/W Force Register Set
       EPwm2Regs.AQCSFRC.bit.CSFA     = 0;          -- Continuous Software Force on output A
       EPwm2Regs.AQCSFRC.bit.CSFB     = 0;          -- Continuous Software Force on output B
     */
    EPwm2Regs.AQCSFRC.all = (EPwm2Regs.AQCSFRC.all & ~0xF) | 0x0;

    /*-- Setup Dead-Band Generator (DB) Submodule --*/
    /* -- Dead-Band Generator Control Register
       EPwm2Regs.DBCTL.bit.OUT_MODE   = 3;          -- Dead Band Output Mode Control
       EPwm2Regs.DBCTL.bit.IN_MODE    = 0;          -- Dead Band Input Select Mode Control
       EPwm2Regs.DBCTL.bit.POLSEL     = 1;          -- Polarity Select Control
     */
    EPwm2Regs.DBCTL.all = (EPwm2Regs.DBCTL.all & ~0x3F) | 0x7;
    EPwm2Regs.DBRED = 144;
    EPwm2Regs.DBFED = 144;

    /*-- Setup Event-Trigger (ET) Submodule --*/
    /* -- Event-Trigger Selection and Event-Trigger Pre-Scale Register
       EPwm2Regs.ETSEL.bit.SOCAEN     = 0;          -- Start of conversion A Enable
       EPwm2Regs.ETSEL.bit.SOCASEL    = 1;          -- Start of conversion A Select
       EPwm2Regs.ETPS.bit.SOCAPRD     = 1;          -- EPWM2SOCA Period Select
       EPwm2Regs.ETSEL.bit.SOCBEN     = 0;          -- Start of conversion B Enable
       EPwm2Regs.ETSEL.bit.SOCBSEL    = 1;          -- Start of conversion B Select
       EPwm2Regs.ETPS.bit.SOCBPRD     = 1;          -- EPWM2SOCB Period Select
       EPwm2Regs.ETSEL.bit.INTEN      = 0;          -- EPWM2INTn Enable
       EPwm2Regs.ETSEL.bit.INTSEL     = 1;          -- EPWM2INTn Select
       EPwm2Regs.ETPS.bit.INTPRD      = 1;          -- EPWM2INTn Period Select
     */
    EPwm2Regs.ETSEL.all = (EPwm2Regs.ETSEL.all & ~0xFF0F) | 0x1101;
    EPwm2Regs.ETPS.all = (EPwm2Regs.ETPS.all & ~0x3303) | 0x1101;

    /*-- Setup PWM-Chopper (PC) Submodule --*/
    /* -- PWM-Chopper Control Register
       EPwm2Regs.PCCTL.bit.CHPEN      = 0;          -- PWM chopping enable
       EPwm2Regs.PCCTL.bit.CHPFREQ    = 0;          -- Chopping clock frequency
       EPwm2Regs.PCCTL.bit.OSHTWTH    = 0;          -- One-shot pulse width
       EPwm2Regs.PCCTL.bit.CHPDUTY    = 0;          -- Chopping clock Duty cycle
     */
    EPwm2Regs.PCCTL.all = (EPwm2Regs.PCCTL.all & ~0x7FF) | 0x0;

    /*-- Set up Trip-Zone (TZ) Submodule --*/
    EALLOW;
    EPwm2Regs.TZSEL.all = 0;

    /* -- Trip-Zone Control Register
       EPwm2Regs.TZCTL.bit.TZA        = 3;          -- TZ1 to TZ6 Trip Action On EPWM2A
       EPwm2Regs.TZCTL.bit.TZB        = 3;          -- TZ1 to TZ6 Trip Action On EPWM2B
     */
    EPwm2Regs.TZCTL.all = (EPwm2Regs.TZCTL.all & ~0xF) | 0xF;

    /* -- Trip-Zone Enable Interrupt Register
       EPwm2Regs.TZEINT.bit.OST       = 0;          -- Trip Zones One Shot Int Enable
       EPwm2Regs.TZEINT.bit.CBC       = 0;          -- Trip Zones Cycle By Cycle Int Enable
     */
    EPwm2Regs.TZEINT.all = (EPwm2Regs.TZEINT.all & ~0x6) | 0x0;
    EDIS;
  }

  /* Start for S-Function (c280xpwm): '<S7>/ePWM1' */

  /*** Initialize ePWM1 modules ***/
  {
    /*-- Setup Time-Base (TB) Submodule --*/
    EPwm1Regs.TBPRD = 7500;

    /* -- Time-Base Control Register
       EPwm1Regs.TBCTL.bit.CTRMODE    = 2;          -- Counter Mode
       EPwm1Regs.TBCTL.bit.SYNCOSEL   = 3;          -- Sync output select
       EPwm1Regs.TBCTL.bit.PRDLD      = 0;          -- Shadow select
       EPwm1Regs.TBCTL.bit.PHSEN      = 0;          -- Phase load enable
       EPwm1Regs.TBCTL.bit.PHSDIR     = 0;          -- Phase Direction
       EPwm1Regs.TBCTL.bit.HSPCLKDIV  = 0;          -- High speed time pre-scale
       EPwm1Regs.TBCTL.bit.CLKDIV     = 0;          -- Timebase clock pre-scale
     */
    EPwm1Regs.TBCTL.all = (EPwm1Regs.TBCTL.all & ~0x3FBF) | 0x32;

    /* -- Time-Base Phase Register
       EPwm1Regs.TBPHS.half.TBPHS     = 0;          -- Phase offset register
     */
    EPwm1Regs.TBPHS.all = (EPwm1Regs.TBPHS.all & ~0xFFFF0000) | 0x0;
    EPwm1Regs.TBCTR = 0x0000;          /* Clear counter*/

    /*-- Setup Counter_Compare (CC) Submodule --*/
    /* -- Counter-Compare Control Register
       EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;  -- Compare A block operating mode.
       EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;  -- Compare B block operating mode.
       EPwm1Regs.CMPCTL.bit.LOADAMODE = 0;          -- Active compare A
       EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;          -- Active compare A
     */
    EPwm1Regs.CMPCTL.all = (EPwm1Regs.CMPCTL.all & ~0x5F) | 0x0;
    EPwm1Regs.CMPA.half.CMPA = 5000;
    EPwm1Regs.CMPB = 6500;

    /*-- Setup Action-Qualifier (AQ) Submodule --*/
    EPwm1Regs.AQCTLA.all = 144;
    EPwm1Regs.AQCTLB.all = 513;

    /* -- Action-Qualifier Software Force Register
       EPwm1Regs.AQSFRC.bit.RLDCSF    = 0;          -- Reload from Shadow options
     */
    EPwm1Regs.AQSFRC.all = (EPwm1Regs.AQSFRC.all & ~0xC0) | 0x0;

    /* -- Action-Qualifier Continuous S/W Force Register Set
       EPwm1Regs.AQCSFRC.bit.CSFA     = 0;          -- Continuous Software Force on output A
       EPwm1Regs.AQCSFRC.bit.CSFB     = 0;          -- Continuous Software Force on output B
     */
    EPwm1Regs.AQCSFRC.all = (EPwm1Regs.AQCSFRC.all & ~0xF) | 0x0;

    /*-- Setup Dead-Band Generator (DB) Submodule --*/
    /* -- Dead-Band Generator Control Register
       EPwm1Regs.DBCTL.bit.OUT_MODE   = 3;          -- Dead Band Output Mode Control
       EPwm1Regs.DBCTL.bit.IN_MODE    = 0;          -- Dead Band Input Select Mode Control
       EPwm1Regs.DBCTL.bit.POLSEL     = 1;          -- Polarity Select Control
     */
    EPwm1Regs.DBCTL.all = (EPwm1Regs.DBCTL.all & ~0x3F) | 0x7;
    EPwm1Regs.DBRED = 144;
    EPwm1Regs.DBFED = 144;

    /*-- Setup Event-Trigger (ET) Submodule --*/
    /* -- Event-Trigger Selection and Event-Trigger Pre-Scale Register
       EPwm1Regs.ETSEL.bit.SOCAEN     = 1;          -- Start of conversion A Enable
       EPwm1Regs.ETSEL.bit.SOCASEL    = 1;          -- Start of conversion A Select
       EPwm1Regs.ETPS.bit.SOCAPRD     = 1;          -- EPWM1SOCA Period Select
       EPwm1Regs.ETSEL.bit.SOCBEN     = 0;          -- Start of conversion B Enable
       EPwm1Regs.ETSEL.bit.SOCBSEL    = 1;          -- Start of conversion B Select
       EPwm1Regs.ETPS.bit.SOCBPRD     = 1;          -- EPWM1SOCB Period Select
       EPwm1Regs.ETSEL.bit.INTEN      = 0;          -- EPWM1INTn Enable
       EPwm1Regs.ETSEL.bit.INTSEL     = 1;          -- EPWM1INTn Select
       EPwm1Regs.ETPS.bit.INTPRD      = 1;          -- EPWM1INTn Period Select
     */
    EPwm1Regs.ETSEL.all = (EPwm1Regs.ETSEL.all & ~0xFF0F) | 0x1901;
    EPwm1Regs.ETPS.all = (EPwm1Regs.ETPS.all & ~0x3303) | 0x1101;

    /*-- Setup PWM-Chopper (PC) Submodule --*/
    /* -- PWM-Chopper Control Register
       EPwm1Regs.PCCTL.bit.CHPEN      = 0;          -- PWM chopping enable
       EPwm1Regs.PCCTL.bit.CHPFREQ    = 0;          -- Chopping clock frequency
       EPwm1Regs.PCCTL.bit.OSHTWTH    = 0;          -- One-shot pulse width
       EPwm1Regs.PCCTL.bit.CHPDUTY    = 0;          -- Chopping clock Duty cycle
     */
    EPwm1Regs.PCCTL.all = (EPwm1Regs.PCCTL.all & ~0x7FF) | 0x0;

    /*-- Set up Trip-Zone (TZ) Submodule --*/
    EALLOW;
    EPwm1Regs.TZSEL.all = 0;

    /* -- Trip-Zone Control Register
       EPwm1Regs.TZCTL.bit.TZA        = 3;          -- TZ1 to TZ6 Trip Action On EPWM1A
       EPwm1Regs.TZCTL.bit.TZB        = 3;          -- TZ1 to TZ6 Trip Action On EPWM1B
     */
    EPwm1Regs.TZCTL.all = (EPwm1Regs.TZCTL.all & ~0xF) | 0xF;

    /* -- Trip-Zone Enable Interrupt Register
       EPwm1Regs.TZEINT.bit.OST       = 0;          -- Trip Zones One Shot Int Enable
       EPwm1Regs.TZEINT.bit.CBC       = 0;          -- Trip Zones Cycle By Cycle Int Enable
     */
    EPwm1Regs.TZEINT.all = (EPwm1Regs.TZEINT.all & ~0x6) | 0x0;
    EDIS;
  }

  /* Start for S-Function (c280xpwm): '<S7>/ePWM3' */

  /*** Initialize ePWM3 modules ***/
  {
    /*-- Setup Time-Base (TB) Submodule --*/
    EPwm3Regs.TBPRD = 7500;

    /* -- Time-Base Control Register
       EPwm3Regs.TBCTL.bit.CTRMODE    = 2;          -- Counter Mode
       EPwm3Regs.TBCTL.bit.SYNCOSEL   = 3;          -- Sync output select
       EPwm3Regs.TBCTL.bit.PRDLD      = 0;          -- Shadow select
       EPwm3Regs.TBCTL.bit.PHSEN      = 0;          -- Phase load enable
       EPwm3Regs.TBCTL.bit.PHSDIR     = 0;          -- Phase Direction
       EPwm3Regs.TBCTL.bit.HSPCLKDIV  = 0;          -- High speed time pre-scale
       EPwm3Regs.TBCTL.bit.CLKDIV     = 0;          -- Timebase clock pre-scale
     */
    EPwm3Regs.TBCTL.all = (EPwm3Regs.TBCTL.all & ~0x3FBF) | 0x32;

    /* -- Time-Base Phase Register
       EPwm3Regs.TBPHS.half.TBPHS     = 0;          -- Phase offset register
     */
    EPwm3Regs.TBPHS.all = (EPwm3Regs.TBPHS.all & ~0xFFFF0000) | 0x0;
    EPwm3Regs.TBCTR = 0x0000;          /* Clear counter*/

    /*-- Setup Counter_Compare (CC) Submodule --*/
    /* -- Counter-Compare Control Register
       EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0;  -- Compare A block operating mode.
       EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0;  -- Compare B block operating mode.
       EPwm3Regs.CMPCTL.bit.LOADAMODE = 0;          -- Active compare A
       EPwm3Regs.CMPCTL.bit.LOADBMODE = 0;          -- Active compare A
     */
    EPwm3Regs.CMPCTL.all = (EPwm3Regs.CMPCTL.all & ~0x5F) | 0x0;
    EPwm3Regs.CMPA.half.CMPA = 5000;
    EPwm3Regs.CMPB = 6500;

    /*-- Setup Action-Qualifier (AQ) Submodule --*/
    EPwm3Regs.AQCTLA.all = 144;
    EPwm3Regs.AQCTLB.all = 513;

    /* -- Action-Qualifier Software Force Register
       EPwm3Regs.AQSFRC.bit.RLDCSF    = 0;          -- Reload from Shadow options
     */
    EPwm3Regs.AQSFRC.all = (EPwm3Regs.AQSFRC.all & ~0xC0) | 0x0;

    /* -- Action-Qualifier Continuous S/W Force Register Set
       EPwm3Regs.AQCSFRC.bit.CSFA     = 0;          -- Continuous Software Force on output A
       EPwm3Regs.AQCSFRC.bit.CSFB     = 0;          -- Continuous Software Force on output B
     */
    EPwm3Regs.AQCSFRC.all = (EPwm3Regs.AQCSFRC.all & ~0xF) | 0x0;

    /*-- Setup Dead-Band Generator (DB) Submodule --*/
    /* -- Dead-Band Generator Control Register
       EPwm3Regs.DBCTL.bit.OUT_MODE   = 3;          -- Dead Band Output Mode Control
       EPwm3Regs.DBCTL.bit.IN_MODE    = 0;          -- Dead Band Input Select Mode Control
       EPwm3Regs.DBCTL.bit.POLSEL     = 1;          -- Polarity Select Control
     */
    EPwm3Regs.DBCTL.all = (EPwm3Regs.DBCTL.all & ~0x3F) | 0x7;
    EPwm3Regs.DBRED = 144;
    EPwm3Regs.DBFED = 144;

    /*-- Setup Event-Trigger (ET) Submodule --*/
    /* -- Event-Trigger Selection and Event-Trigger Pre-Scale Register
       EPwm3Regs.ETSEL.bit.SOCAEN     = 0;          -- Start of conversion A Enable
       EPwm3Regs.ETSEL.bit.SOCASEL    = 1;          -- Start of conversion A Select
       EPwm3Regs.ETPS.bit.SOCAPRD     = 1;          -- EPWM3SOCA Period Select
       EPwm3Regs.ETSEL.bit.SOCBEN     = 0;          -- Start of conversion B Enable
       EPwm3Regs.ETSEL.bit.SOCBSEL    = 1;          -- Start of conversion B Select
       EPwm3Regs.ETPS.bit.SOCBPRD     = 1;          -- EPWM3SOCB Period Select
       EPwm3Regs.ETSEL.bit.INTEN      = 0;          -- EPWM3INTn Enable
       EPwm3Regs.ETSEL.bit.INTSEL     = 1;          -- EPWM3INTn Select
       EPwm3Regs.ETPS.bit.INTPRD      = 1;          -- EPWM3INTn Period Select
     */
    EPwm3Regs.ETSEL.all = (EPwm3Regs.ETSEL.all & ~0xFF0F) | 0x1101;
    EPwm3Regs.ETPS.all = (EPwm3Regs.ETPS.all & ~0x3303) | 0x1101;

    /*-- Setup PWM-Chopper (PC) Submodule --*/
    /* -- PWM-Chopper Control Register
       EPwm3Regs.PCCTL.bit.CHPEN      = 0;          -- PWM chopping enable
       EPwm3Regs.PCCTL.bit.CHPFREQ    = 0;          -- Chopping clock frequency
       EPwm3Regs.PCCTL.bit.OSHTWTH    = 0;          -- One-shot pulse width
       EPwm3Regs.PCCTL.bit.CHPDUTY    = 0;          -- Chopping clock Duty cycle
     */
    EPwm3Regs.PCCTL.all = (EPwm3Regs.PCCTL.all & ~0x7FF) | 0x0;

    /*-- Set up Trip-Zone (TZ) Submodule --*/
    EALLOW;
    EPwm3Regs.TZSEL.all = 0;

    /* -- Trip-Zone Control Register
       EPwm3Regs.TZCTL.bit.TZA        = 3;          -- TZ1 to TZ6 Trip Action On EPWM3A
       EPwm3Regs.TZCTL.bit.TZB        = 3;          -- TZ1 to TZ6 Trip Action On EPWM3B
     */
    EPwm3Regs.TZCTL.all = (EPwm3Regs.TZCTL.all & ~0xF) | 0xF;

    /* -- Trip-Zone Enable Interrupt Register
       EPwm3Regs.TZEINT.bit.OST       = 0;          -- Trip Zones One Shot Int Enable
       EPwm3Regs.TZEINT.bit.CBC       = 0;          -- Trip Zones Cycle By Cycle Int Enable
     */
    EPwm3Regs.TZEINT.all = (EPwm3Regs.TZEINT.all & ~0x6) | 0x0;
    EDIS;
  }

  /* Start for S-Function (c280xpwm): '<S7>/ePWM4' */

  /*** Initialize ePWM6 modules ***/
  {
    /*-- Setup Time-Base (TB) Submodule --*/
    EPwm6Regs.TBPRD = 7500;

    /* -- Time-Base Control Register
       EPwm6Regs.TBCTL.bit.CTRMODE    = 2;          -- Counter Mode
       EPwm6Regs.TBCTL.bit.SYNCOSEL   = 3;          -- Sync output select
       EPwm6Regs.TBCTL.bit.PRDLD      = 0;          -- Shadow select
       EPwm6Regs.TBCTL.bit.PHSEN      = 0;          -- Phase load enable
       EPwm6Regs.TBCTL.bit.PHSDIR     = 0;          -- Phase Direction
       EPwm6Regs.TBCTL.bit.HSPCLKDIV  = 0;          -- High speed time pre-scale
       EPwm6Regs.TBCTL.bit.CLKDIV     = 0;          -- Timebase clock pre-scale
     */
    EPwm6Regs.TBCTL.all = (EPwm6Regs.TBCTL.all & ~0x3FBF) | 0x32;

    /* -- Time-Base Phase Register
       EPwm6Regs.TBPHS.half.TBPHS     = 0;          -- Phase offset register
     */
    EPwm6Regs.TBPHS.all = (EPwm6Regs.TBPHS.all & ~0xFFFF0000) | 0x0;
    EPwm6Regs.TBCTR = 0x0000;          /* Clear counter*/

    /*-- Setup Counter_Compare (CC) Submodule --*/
    /* -- Counter-Compare Control Register
       EPwm6Regs.CMPCTL.bit.SHDWAMODE = 0;  -- Compare A block operating mode.
       EPwm6Regs.CMPCTL.bit.SHDWBMODE = 0;  -- Compare B block operating mode.
       EPwm6Regs.CMPCTL.bit.LOADAMODE = 0;          -- Active compare A
       EPwm6Regs.CMPCTL.bit.LOADBMODE = 0;          -- Active compare A
     */
    EPwm6Regs.CMPCTL.all = (EPwm6Regs.CMPCTL.all & ~0x5F) | 0x0;
    EPwm6Regs.CMPA.half.CMPA = 5000;
    EPwm6Regs.CMPB = 6500;

    /*-- Setup Action-Qualifier (AQ) Submodule --*/
    EPwm6Regs.AQCTLA.all = 144;
    EPwm6Regs.AQCTLB.all = 513;

    /* -- Action-Qualifier Software Force Register
       EPwm6Regs.AQSFRC.bit.RLDCSF    = 0;          -- Reload from Shadow options
     */
    EPwm6Regs.AQSFRC.all = (EPwm6Regs.AQSFRC.all & ~0xC0) | 0x0;

    /* -- Action-Qualifier Continuous S/W Force Register Set
       EPwm6Regs.AQCSFRC.bit.CSFA     = 0;          -- Continuous Software Force on output A
       EPwm6Regs.AQCSFRC.bit.CSFB     = 0;          -- Continuous Software Force on output B
     */
    EPwm6Regs.AQCSFRC.all = (EPwm6Regs.AQCSFRC.all & ~0xF) | 0x0;

    /*-- Setup Dead-Band Generator (DB) Submodule --*/
    /* -- Dead-Band Generator Control Register
       EPwm6Regs.DBCTL.bit.OUT_MODE   = 3;          -- Dead Band Output Mode Control
       EPwm6Regs.DBCTL.bit.IN_MODE    = 0;          -- Dead Band Input Select Mode Control
       EPwm6Regs.DBCTL.bit.POLSEL     = 1;          -- Polarity Select Control
     */
    EPwm6Regs.DBCTL.all = (EPwm6Regs.DBCTL.all & ~0x3F) | 0x7;
    EPwm6Regs.DBRED = 144;
    EPwm6Regs.DBFED = 144;

    /*-- Setup Event-Trigger (ET) Submodule --*/
    /* -- Event-Trigger Selection and Event-Trigger Pre-Scale Register
       EPwm6Regs.ETSEL.bit.SOCAEN     = 0;          -- Start of conversion A Enable
       EPwm6Regs.ETSEL.bit.SOCASEL    = 1;          -- Start of conversion A Select
       EPwm6Regs.ETPS.bit.SOCAPRD     = 1;          -- EPWM6SOCA Period Select
       EPwm6Regs.ETSEL.bit.SOCBEN     = 0;          -- Start of conversion B Enable
       EPwm6Regs.ETSEL.bit.SOCBSEL    = 1;          -- Start of conversion B Select
       EPwm6Regs.ETPS.bit.SOCBPRD     = 1;          -- EPWM6SOCB Period Select
       EPwm6Regs.ETSEL.bit.INTEN      = 0;          -- EPWM6INTn Enable
       EPwm6Regs.ETSEL.bit.INTSEL     = 1;          -- EPWM6INTn Select
       EPwm6Regs.ETPS.bit.INTPRD      = 1;          -- EPWM6INTn Period Select
     */
    EPwm6Regs.ETSEL.all = (EPwm6Regs.ETSEL.all & ~0xFF0F) | 0x1101;
    EPwm6Regs.ETPS.all = (EPwm6Regs.ETPS.all & ~0x3303) | 0x1101;

    /*-- Setup PWM-Chopper (PC) Submodule --*/
    /* -- PWM-Chopper Control Register
       EPwm6Regs.PCCTL.bit.CHPEN      = 0;          -- PWM chopping enable
       EPwm6Regs.PCCTL.bit.CHPFREQ    = 0;          -- Chopping clock frequency
       EPwm6Regs.PCCTL.bit.OSHTWTH    = 0;          -- One-shot pulse width
       EPwm6Regs.PCCTL.bit.CHPDUTY    = 0;          -- Chopping clock Duty cycle
     */
    EPwm6Regs.PCCTL.all = (EPwm6Regs.PCCTL.all & ~0x7FF) | 0x0;

    /*-- Set up Trip-Zone (TZ) Submodule --*/
    EALLOW;
    EPwm6Regs.TZSEL.all = 0;

    /* -- Trip-Zone Control Register
       EPwm6Regs.TZCTL.bit.TZA        = 3;          -- TZ1 to TZ6 Trip Action On EPWM6A
       EPwm6Regs.TZCTL.bit.TZB        = 3;          -- TZ1 to TZ6 Trip Action On EPWM6B
     */
    EPwm6Regs.TZCTL.all = (EPwm6Regs.TZCTL.all & ~0xF) | 0xF;

    /* -- Trip-Zone Enable Interrupt Register
       EPwm6Regs.TZEINT.bit.OST       = 0;          -- Trip Zones One Shot Int Enable
       EPwm6Regs.TZEINT.bit.CBC       = 0;          -- Trip Zones Cycle By Cycle Int Enable
     */
    EPwm6Regs.TZEINT.all = (EPwm6Regs.TZEINT.all & ~0x6) | 0x0;
    EDIS;
  }

  /* Start for S-Function (c280xgpio_do): '<S7>/Digital Output1' */
  EALLOW;
  GpioCtrlRegs.GPAMUX2.all &= 0xFFFFFFCFU;
  GpioCtrlRegs.GPADIR.all |= 0x40000U;
  EDIS;

  /* End of SystemInitialize for S-Function (c28xisr_c2000): '<S1>/C28x Hardware Interrupt' */
  MCU_28335_DW.tmr1msbase = 0U;

  /* SystemInitialize for Chart: '<Root>/TimerBase' incorporates:
   *  SubSystem: '<Root>/Application'
   */
  MCU_28335_DW.tmr10msbase = 0U;

  /* Start for S-Function (c280xgpio_do): '<S8>/Digital Output1' */
  EALLOW;
  GpioCtrlRegs.GPCMUX1.all &= 0xFFFFFCFFU;
  GpioCtrlRegs.GPCDIR.all |= 0x10U;
  EDIS;

  /* ConstCode for S-Function (c28xisr_c2000): '<S1>/C28x Hardware Interrupt' incorporates:
   *  SubSystem: '<S1>/Function-Call Subsystem'
   */

  /* ConstCode for function-call system: '<S1>/Function-Call Subsystem' */

  /* ConstCode for S-Function (c280xpwm): '<S7>/ePWM2' incorporates:
   *  Constant: '<S7>/Constant1'
   */

  /*-- Update CMPA value for ePWM2 --*/
  {
    EPwm2Regs.CMPA.half.CMPA = (uint16_T)((5000.0));
  }

  /* ConstCode for S-Function (c280xpwm): '<S7>/ePWM1' incorporates:
   *  Constant: '<S7>/Constant2'
   */

  /*-- Update CMPA value for ePWM1 --*/
  {
    EPwm1Regs.CMPA.half.CMPA = (uint16_T)((3000.0));
  }

  /* ConstCode for S-Function (c280xpwm): '<S7>/ePWM3' incorporates:
   *  Constant: '<S7>/Constant3'
   */

  /*-- Update CMPA value for ePWM3 --*/
  {
    EPwm3Regs.CMPA.half.CMPA = (uint16_T)((5000.0));
  }

  /* End of ConstCode for S-Function (c28xisr_c2000): '<S1>/C28x Hardware Interrupt' */
}

/* Model terminate function */
void MCU_28335_terminate(void)
{
  /* (no terminate code required) */
}

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
